No RISC No Fun

CPU buses and attachments

5 June 2009

HP used various CPU bus designs to attach the main processor to the main system bus with its I/O adapters and the memory. About five main connection strategies and buses were used, which were added as CPU attachment subsections to new or updated bus entries.

1. SMB bus attachment on early 32-bit PA-RISC 1.0 CPUs from the 1980s
2. PBus on 32-bit PA-RISC 1.1 PA-7000 and PA-7100
3. Direct attachments to the GSC bus on the low-cost PA-RISC 1.1 LC processors have
4. Runway bus attachments on PA-7200 and 64-bit PA-8000/PA-8200 processors
5. Runway+/Runway DDR , an advanced Runway variant, on PA-8500, PA-8600 and PA-8700
6. The last PA-RISC processors, the dual-core PA-8800 and PA-8900 use Itanium 2 processor buses

The PA-RISC processors sections have been updated with the bus information as well.

Memory and I/O controllers

5 June 2009

Several forms of memory and I/O controllers (MIOCs) were employed on HP PA-RISC systems. The chipsets page has several updated and new sections:

• In early days (NS-1, NS-2 and PCX processors) a combination of support chips for the CPU was used — the SIU/SPI controllers being the main memory and bus controllers
• Later on, these chips were integrated into Viper, a single MIOC controller (PA-7000/PA-7100)
• On the LC processors the controller moved as integrated MIOC onto the CPU die (PA-7100LC/PA-7300LC)
• Newer Runway-based CPUs (PA-7200, PA-8000/PA-8200) split the MIOC again in different external chips, the U2/UTurn I/O controllers and MMC/SMC memory controllers
• Later 64-bit processors (PA-8500, PA-8600 and PA-8700) use a newer Runway+/Runway DDR variant and several I/O and memory controllers, such as Astro, Stretch or Cell
• The newest 64-bit processors (PA-8800, PA-8900 and Itaniums) use Itanium chipsets, including the HP zx1