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PA-RISC Buses

Overview

Buses used in PA-RISC computers overview
Type Frequency
max		 Width Data rate
max		 Usage
EISA 8.3 MHz 32-bit 33 MB/s Expansion, devices
SGC 25 MHz? 32-bit 100 MB/s Expansion, devices
HP-PB 8 MHz 32-bit 32 MB/s Expansion, devices
PCI-32 66 MHz 32-bit 266 MB/s Expansion, devices
PCI-64 66 MHz 64-bit 533 MB/s Expansion, devices
PCI-X 133 MHz 64-bit 1066 MB/s Expansion, devices
GSC 40 MHz 32-bit 160 MB/s CPU, system, expansion, devices
HSC/GSC+ 40 MHz 32-bit 160 MB/s System, expansion, devices
GSC-2 40 MHz? 32-bit DDR 256 MB/s Expansion, devices
VSC PA-7000 60 MHz 32-bit 240 MB/s System, expansion, devices
VSC PA-7100 60 MHz 64-bit 480 MB/s System
SMB 30 MHz 64-bit ? System
PBus 66 MHz? 64-bit CPU
Runway 120 MHz 64-bit 960 MB/s CPU
Runway+/DDR 125 MHz 64-bit ~2 GB/s CPU

EISA

Extended ISA (EISA) is an device I/O and expansion bus that replaced the 1980s ISA bus in HP Unix workstations and servers. EISA buses are found in various early 32-bit workstations, either on-board or through a bus converter; this industry standard bus made it possible to use third-party, generic expansion cards such as network interfaces and SCSI controllers.

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SGC

System Graphics Connect (SGC) is the main system bus of earlier 32-bit series 700 workstations. The I/O controller, CPU/memory controller and expansion cards attach to the GSC bus in these systems. Expansion cards are available in two different form factors: EISA and DIO.

References

  1. HP-UX Workstation HCL (Hardware Compatibility List) PA-RISC (p. 195) Hewlett-Packard Company (July 1998, 14th ed.)

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HP-PB

HP-Precision Bus (HP-PB, sometimes HP/PB) is the I/O bus in many older 32-bit HP servers. Two form factors/sizes of HP-PB expansion cards were sold: single and double.

References

  1. HP-UX Workstation HCL (Hardware Compatibility List) PA-RISC (p. 190) Hewlett-Packard Company (July 1998, 14th ed.)

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PCI

With PCI HP changed its HP 9000 workstation and server design to an industry standard expansion and device bus. This allowed for using more off-the-shelf I/O chips and cards. Some of HP’s PCI expansion cards for HP 9000 computers are actually relabeled third-party products or OEM designs with a PA-RISC compatible firmware and HP-UX driver.

Proper HP-UX drivers are the limiting factor for generic third-party PCI expansion cards in PA-RISC systems. In most cases drivers are only available for the HP-branded products. Open source operating systems as Linux or OpenBSD support many more devices in their PA-RISC ports, since many drivers were taken over from other architectures.

PCI buses used in PA-RISC computers overview
PCI Clock Width Data rate
max		 Signalling
PCI-32/33 33 MHz 32-bit 133 MB/s 3.3 V/5 V
PCI-32/66 66 MHz 32-bit 266 MB/s 3.3 V
PCI-64/33 33 MHz 64-bit 266 MB/s 3.3 V/5 V
PCI-64/66 66 MHz 64-bit 533 MB/s 3.3 V
PCI-X 66 MHz 64-bit 533 MB/s ?
PCI-X 100 MHz 64-bit 800 MB/s 3.3 V
PCI-X 133 MHz 64-bit 1066 MB/s ?

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GSC

The General System Connect (GSC) bus is the primary system and I/O bus on most of second-generation 32-bit HP 9000 workstations. GSC connects most of the I/O devices to the central system bus and chipset, with some CPUs attaching directly to it (PA-7100LC and PA-7300LC; see below). HSC is a variant of GSC but electronically the same bus.

GSC bus features

Bus variants

  1. Original GSC (GSC-1X) with maximum clock of 40 MHz and peak data rate of 160 MHz, used on most of the early GSC systems, mostly together with LASI as main I/O controller
  2. GSC+/HSC (Extended GSC) with a maximum clock of 40 MHz and peak data rates of 160 MB/s (132 MB/s with 33 MHz, 144 MB/s with 36 MHz)
  3. GSC-1.5X with additional extended write operations
  4. GSC-2 (GSC-2X) with a peak data rate of 256 MB/s on 64-bit systems with the UTurn I/O bridge (to Runway)

Expansion cards variants

CPU attachments

On the two 32-bit LC Low Cost processors PA-7100LC and PA-7300LC GSC is the main system bus. The CPUs integrate the external memory and I/O controller (MIOC) onto the processor (mostly used with LASI chipsets), with memory and cache directly attaching to it.

  1. MIOC, main memory and I/O controller, directly integrated on the CPU
    • Execution units and internal caches attach on-chip to the MIOC
    • External cache and memory attach to MIOC
  2. GSC, system main bus, attaches to MIOC and I/O controllers
    • Attaches via 32-bit
    • PA-7300LC systems use extended GSC+
  3. I/O adapters attach to GSC
    • LASI chipset
    • Some video adapters directly attach to GSC
    • I/O slots extend GSC
    • Bus adapters, including EISA, VME and PCI, attach to GSC (includes WAX — a modified LASI —, Dino, and custom chips)

View a system-level illustration (ASCII).

References

  1. An I/O System on a Chip Thomas V. Spencer et al (April 1995, Hewlett-Packard Journal)
  2. PA-RISC Linux: Glossary The PARISC-Linux Project (May 2005)
  3. HP-UX Workstation HCL (Hardware Compatibility List) PA-RISC (pp. 188-189, 191, 198) Hewlett-Packard Company (July 1998, 14th ed.)

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VSC

Viper System Connect (VSC) is the central system bus of computers with PA-7000 or PA-7100 processors. It connects the Viper central bus controller (also known as MIOC, PMI or PIC) to the memory and I/O buses (the latter via adapters). In multiprocessor configurations, each processor has its own Viper controller, which then in turn connects to a shared VSC bus with attachments to all Viper controllers, memory and I/O converters. VSC is also known as P MB (Processor Memory Bus) especially on multi-processor configurations.

References

  1. Corporate Business Servers: An Alternative to Mainframes for Business Computing (.pdf) Thomas B. Alexander et al (June 1994: Hewlett-Packard Journal)

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System Main Bus (SMB)

In early 1980s PA-RISC 1.0 systems the NS-1, NS-2 and PCX processors attach to the System Main Bus (SMB), via bus converters.

Bus features

CPU attachment

  1. System controllers (SIU or SPI) attach the CPU with its execution units to the SMB system main bus
  2. System Main Bus (SMB) is the central bus, to which CPU, memory and I/O buses attach
    • CPU attaches via SIU/SPU to SMB with 64-bit at 25-30 MHz
    • Memory attaches to SMB
    • Some: Memory extensions attach to SMB (via MABs; see below)
  3. Central Bus/Midbus (CTB) attaches the I/O via bus convertes to SMB
    • Attaches via 32-bit at maximum of 10 MHz at SMB
    • Two CTBs per SMB
  4. CIO buses, up to three, attach via adapters to CTB
    • Attaches via 16-bit at 4 MHz (probably dependant on CTB clock)
    • I/O expansion cards plug into CIO slots
  5. Some systems only: Memory Array Buses (MABs) attach to SMB for more memory
    • Attaches via 64-bit (with ECC 72-bit) at SMB

View a system-level illustration (ASCII).

The TS-1, the first PA-RISC processor used a simpler version of this setup and directly attached the CPU to the Central Bus (CTB) with 32-bit at 8 MHz. Here, all the CPU, memory and I/O devices directly connect to the CTB.

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PBus

Systems with PA-7000 or PA-7100/PA-7150 processors use the PBus processor bus between the CPU and external memory controller (Viper). These systems with the VSC main bus mostly use ASP chipsets for system I/O and devices. On multi-processor systems with a PA-7100 two attachment variants are possible — either shared memory controller (two processors) or shared system bus (up to eight processors).

Bus features

CPU attachment

  1. PBus is the main processor and memory bus
    • CPU attaches to PBus with 32-bit (with ECC 40-bit)
  2. Viper, the main memory and I/O controller attaches to PBus
    • Memory attaches to MIOC via 64-bit (with ECC 72-bit)
  3. VSC, the system main bus, attaches to MIOC and various I/O controllers
    • Attaches via 32-bit (PA-7000) or 64-bit (PA-7100) at MIOC
  4. I/O adapters attach to VSC

View a system-level illustration (ASCII) (single-processor).

Multiprocessor attachment

  1. Two-way SMP (Low Cost): Two CPUs share a PBus and attach to the same MIOC. Memory attaches directly to MIOC, I/O attaches via VSC to MIOC.
  2. Scalable MP: Each CPU has its own MIOC. All MIOCs in the system share a VSC bus, to which I/O and memory attach.

View a system-level illustration (ASCII) (PA-7100 multi-processor).

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Runway

Runway is the system bus of newer 64-bit systems with PA-7200 and PA-8000 processors and up. It is a synchronous, split-transaction bus. PA-8500, PA-8600 and PA-8700 use an advanced version of Runway, Runway+/Runway DDR.

Bus features

Runway CPU attachments

The PA-7200, PA-8000 and PA-8200 processors with the Runway bus use split I/O and memory controllers — the U2/UTurn I/O Adapters (IOAs) and MMC/SMC memory controllers with each what can be called frontends and backends, with the former interfacing to the CPU and its processor bus and the latter attaching the frontend to customized bus attachments on their external side. This allowed HP to use the frontend parts of these chipsets with a variety of different system design which only required modified backend parts for new memory or I/O technologies.

  1. Runway is the main processor and memory bus
    • 1-4 CPUs attach to Runway with 64-bit, parity-protected
    • SMP-capable
  2. MMC is the main memory controller which attaches to Runway
    • Master Memory Controller (MMC)
    • Attaches to Runway with 64-bit (with example of 120 MHz at a data rate of 960 MB/s peak)
    • Memory attaches to MMC via slave Memory Controllers (SMC) and Data Multiplexers, 128-bit 60 MHz data (ECC) and 39-bit 60 MHz address buses
  3. U2/UTurn I/O adapters attach the main I/O bus and system to the Runway processor bus
    • Attach to Runway with 64-bit
    • Two I/O adapters (IOAs) per U2/UTurn chip
    • Maximum data rate depends on Runway clock with 120 MHz and 64-bit: 960 MB/s
  4. GSC+, the main system bus, attach to the U2/UTurn IOAs
    • Attaches via 32-bit at a fraction of Runway/IOA clock, mostly 40 MHz
    • PA-7300LC systems use the extended GSC version
  5. I/O adapters and slots attach to GSC+
    • LASI chipset
    • Video adapters
    • I/O slots extend GSC
    • Bus adapters, including EISA, VME and PCI, attach to GSC+

Runway+/Runway DDR CPU attachments

The PA-8500, PA-8600, PA-8700 processors use an advanced version of the Runway system bus with increased data rate and utilized different I/O and memory controllers, with most using the Astro chipset (IOMMU) and few servers the sophisticated Stretch and Cell chipsets.

Described below is the common configuration with Astro chipset — for the Stretch/Cell bus attachments see their entries at the Chipset page.

  1. Runway+/Runway DDR is the main processor and memory bus
    • 1-4 CPUs attach to Runway with 64-bit, parity-protected
    • SMP-capable
  2. Astro is the main memory and I/O controller which attaches to Runway
    • Attaches to Runway+/Runway DDR with 64-bit at maximum of 125 MHz (with in this case 2.0 GB/s peak data rate)
    • Memory attaches to Astro with a peak data rate of about 2.0 GB/s at 125 MHz
    • Up to eight I/O links (ropes) with each 250 MB/s attach to Astro
  3. Elroy I/O adapters attach PCI bridges via the I/O ropes to Astro
    • One or two ropes per Elroy PCI bridge
    • PCI slots or devices attach to Elroy bridges
  4. PCI, the main I/O buses, attach to the multiple Elroy bridges
    • 33 or 66 MHz, 32 or 64-bit
  5. I/O devices, adapters and slots attach to PCI

References

  1. A High-Performance, Low-Cost Multiprocessor Bus for Workstations and Midrange Servers William R. Bryg, Kenneth K. Chan, and Nicholas S. Fiduccia (February 1996: Hewlett-Packard Journal)

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