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PA-RISC Buses

EISA

The Extended ISA bus replaced ISA in HP Unix systems. EISA buses are available in several older 32-bit workstations, either on-board or through a converter, which made it possible to use third-party, generic expansion cards.

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SGC

The System Graphics Connect is the main system bus of the older 32-bit series 700 workstations. Thus SGC expansion cards directly attach to the main bus in these systems. Cards were manufactured in two different form factors/sizes: EISA and DIO.

References

  1. HP-UX Workstation HCL (Hardware Compatibility List) PA-RISC (p. 195) Hewlett-Packard Company (July 1998, 14th ed.)

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HP-PB

The HP-Precision Bus is the I/O bus in many older 32-bit series 800 servers. There are two form factors/sizes of HP-PB expansion cards: single and double.

References

  1. HP-UX Workstation HCL (Hardware Compatibility List) PA-RISC (p. 190) Hewlett-Packard Company (July 1998, 14th ed.)

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PCI

With the PCI bus HP changed the HP 9000 design to use an industry standard expansion and device bus. This made it possible to use cheaper COTS products such as I/O chips and cards without having to build (HP-proprietary) GSC/SGC interfaces. Some of HP’s PCI expansion cards for HP 9000 computers are relabeled third-party products or OEM designs with a PA-RISC compatible firmware and HP-UX driver.

Proper HP-UX drivers are the limiting factor for generic third-party PCI expansion cards in PA-RISC systems. In most cases HP supplied drivers only for their own HP-branded products. This prevents using common storage or networking adapters from the PC world, since no proper HP-UX drivers are available.

Open source operating systems as Linux or OpenBSD support much more varied expansion cards on their PA-RISC ports, since many drivers could be ported or taken over from other architectures.

PCI buses used in PA-RISC computers overview
PCI Clock Width Data rate
max		 Signalling
PCI-32/33 33MHz 32-bit 133MB/s 3.3V/5V
PCI-32/66 66MHz 32-bit 266MB/s 3.3V
PCI-64/33 33MHz 64-bit 266MB/s 3.3V/5V
PCI-64/66 66MHz 64-bit 533MB/s 3.3V
PCI-X 66MHz 64-bit 533MB/s ?
PCI-X 100MHz 64-bit 800MB/s 3.3V
PCI-X 133MHz 64-bit 1066MB/s ?

Any PCI card should run in any PCI slot if the voltage (3.3V or 5V) is correct. Slower cards in faster slots will reduce the overall PCI bandwidth of that particular bus.

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GSC/HSC

The General System Connect bus is the primary system and I/O bus on most of the older, numbered HP 9000/700 workstations. It connects most of the I/O devices to the system bus and central chipset. Some CPUs directly attach to GSC (PA-7100LC and PA-7300LC; see below). HSC is a variant of GSC but electronically the same bus.

GSC bus features

Bus variants

  1. Original GSC (GSC-1X) with peak data rate 142MB/s
  2. GSC+ (Extended GSC) with a maximum clock of 40MHz and peak data rates of 160MB/s (132MB/s with 33MHz, 144MB/s with 36MHz)
  3. GSC-1.5X with additional extended write operations
  4. GSC-2x with a peak data rate of 256MB/s

Expansion cards variants

CPU attachments

The two 32-bit LC Low Cost processors PA-7100LC and PA-7300LC integrate the previously external memory and I/O controller (MIOC) on the processor itself. This allowed for the processor to directly attach to the main system bus, in this case the GSC bus (which mostly was used with LASI chipsets). Memory and cache directly attach to the processor with its integrated MIOC. Both PA-7100LC and PA-7300LC were not multi-processor capable.

  1. MIOC is the main memory and I/O controller directly integrated on the CPU
    • Execution units and internal caches attach on-chip to the MIOC
    • External cache and memory attach to MIOC
  2. GSC, the system main bus, attaches to MIOC and various I/O controllers
    • Attaches via 32-bit
    • PA-7300LC systems use the extended GSC+
  3. I/O adapters attach to GSC
    • LASI chipset
    • Some video adapters directly attach to GSC
    • I/O slots extend GSC
    • Bus adapters, including EISA, VME and PCI, attach to GSC (includes WAX — a modified LASI —, Dino, and custom chips)

View a system-level illustration (ASCII).

References

  1. PA-RISC Linux: Glossary The PARISC-Linux Project (May 2005)
  2. HP-UX Workstation HCL (Hardware Compatibility List) PA-RISC (pp. 188-189, 191, 198)
  3. Hewlett-Packard Company (July 1998, 14th ed.)

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VSC

The Viper System Connect bus is the central system bus of computers with the PA-7000 or PA-7100 processors. It connects the Viper central bus controller (known as MIOC, PMI or PIC, interfaces to the main processor) to the memory and I/O buses (via adapters). In multiprocessor configurations, each processor has its own Viper controller, which then in turn connect to a shared VSC bus, which has attachments to all Viper controllers, the memory and the I/O converters. It is also known as PMB — Processor Memory Bus — especially on multi-processor configurations.

References

  1. Corporate Business Servers: An Alternative to Mainframes for Business Computing (.pdf) Thomas B. Alexander et al (June 1994: Hewlett-Packard Journal)

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System Main Bus (SMB)

In early PA-RISC (1.0) systems with the NS-1, NS-2 and PCX processors the CPU attaches via bus converters to the System Main Bus.

Bus features

CPU attachment

  1. System controllers (SIU or SPI) attach the CPU with its execution units to the SMB system main bus
  2. System Main Bus (SMB) is the central bus, to which CPU, memory and I/O buses attach
    • CPU attaches via SIU/SPU to SMB with 64-bit at 25-30MHz
    • Memory attaches to SMB
    • (Some) Memory extensions attach to SMB (via MABs; see below)
  3. Central Bus/Midbus (CTB) attaches the I/O via bus convertes to SMB
    • Attaches via 32-bit at maximum of 10MHz at SMB
    • Two CTBs per SMB
  4. CIO buses (up to three) attach via adapters to CTB
    • Attaches via 16-bit at 4MHz (probably dependant on CTB clock)
    • I/O expansion cards plug into CIO slots
  5. (Some systems only) Memory Array Buses (MABs) attach to SMB for more memory
    • Attaches via 72-bit (ECC) at SMB

View a system-level illustration (ASCII).

The TS-1, the first PA-RISC processor used a simpler version of this setup and directly attached the CPU to the Central Bus (CTB) with 32-bit at 8MHz. Here, all the CPU, memory and I/O devices directly connect to the CTB.

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PBus

Systems with PA-7000 or PA-7100/PA-7150 processors use the PBus processor bus between the CPU itself and the external memory controller (Viper). These system with VSC main bus mostly used ASP chipsets. On multi-processor systems with a PA-7100, two attachment variants were possible — either with a shared memory controller (two processors) or with a shared system bus (up to eight processors).

Bus features

CPU attachment

  1. PBus is the main processor and memory bus
    • CPU attaches to PBus with 32-bit
  2. Viper, the main memory and I/O controller attaches to PBus
    • Memory attaches to MIOC via 72-bit (64-bit with ECC)
  3. VSC, the system main bus, attaches to MIOC and various I/O controllers
    • Attaches via 32-bit (PA-7000) or 64-bit (PA-7100) at MIOC
  4. I/O adapters attach to VSC

View a system-level illustration (ASCII) (single-processor).

Multiprocessor attachment

  1. Two-way SMP (Low Cost): Two CPUs share a PBus and attach to the same MIOC. Memory attaches directly to MIOC, I/O attaches via VSC to MIOC.
  2. Scalable MP: Each CPU has its own MIOC. All MIOCs in the system share a VSC bus, to which I/O and memory attach.

View a system-level illustration (ASCII) (PA-7100 multi-processor).

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Runway

Runway is the system bus of newer 64-bit systems with PA-7200 and PA-8000 processors and up. It is a synchronous, split-transaction bus. PA-8500, PA-8600 and PA-8700 use an advanced version of Runway, Runway+/Runway DDR.

Bus features

Runway CPU attachments

The PA-7200, PA-8000 and PA-8200 processors with the Runway bus use split I/O and memory controllers — the U2/UTurn I/O Adapters (IOAs) and MMC/SMC memory controllers with each what can be called frontends and backends, with the former interfacing to the CPU and its processor bus and the latter attaching the frontend to customized bus attachments on their external side. This allowed HP to use the frontend parts of these chipsets with a variety of different system design which only required modified backend parts for new memory or I/O technologies.

  1. Runway is the main processor and memory bus
    • 1-4 CPUs attach to Runway with 64-bit, parity-protected
    • SMP-capable
  2. MMC is the main memory controller which attaches to Runway
    • Master Memory Controller (MMC)
    • Attaches to Runway with 64-bit (with example of 120MHz at a data rate of 960MB/s raw)
    • Memory attaches to MMC via slave Memory Controllers (SMC) and Data Multiplexers, 128-bit 60MHz data (ECC) and 39-bit 60MHz address buses
  3. U2/UTurn I/O adapters attach the main I/O bus and system to the Runway processor bus
    • Attach to Runway with 64-bit
    • Two I/O adapters (IOAs) per U2/UTurn chip
    • Maximum data rate depends on Runway clock with 120MHz and 64-bit: 960MB/s
  4. GSC+, the main system bus, attach to the U2/UTurn IOAs
    • Attaches via 32-bit at a fraction of Runway/IOA clock, mostly 40MHz
    • PA-7300LC systems use the extended GSC version
  5. I/O adapters and slots attach to GSC+
    • LASI chipset
    • Video adapters
    • I/O slots extend GSC
    • Bus adapters, including EISA, VME and PCI, attach to GSC+

Runway+/Runway DDR CPU attachments

The PA-8500, PA-8600, PA-8700 processors use an advanced version of the Runway system bus with increased data rate and utilized different I/O and memory controllers, with most using the Astro chipset (IOMMU) and few servers the sophisticated Stretch and Cell chipsets.

Described below is the common configuration with Astro chipset — for the Stretch/Cell bus attachments see their entries at the Chipset page.

  1. Runway+/Runway DDR is the main processor and memory bus
    • 1-4 CPUs attach to Runway with 64-bit, parity-protected
    • SMP-capable
  2. Astro is the main memory and I/O controller which attaches to Runway
    • Attaches to Runway+/Runway DDR with 64-bit at maximum of 125MHz (with in this case 2.0GB/s peak data rate)
    • Memory attaches to Astro with a peak data rate of about 2.0GB/s at 125MHz
    • Up to eight I/O links (ropes) with each 250MB/s attach to Astro
  3. Elroy I/O adapters attach PCI bridges via the I/O ropes to Astro
    • One or two ropes per Elroy PCI bridge
    • PCI slots or devices attach to Elroy bridges
  4. PCI, the main I/O buses, attach to the multiple Elroy bridges
    • 33 or 66MHz, 32 or 64-bit
  5. I/O devices, adapters and slots attach to PCI

References

  1. A High-Performance, Low-Cost Multiprocessor Bus for Workstations and Midrange Servers William R. Bryg, Kenneth K. Chan, and Nicholas S. Fiduccia (February 1996: Hewlett-Packard Journal)

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