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PA-RISC Chipsets

Overview

Most HP PA-RISC computers use proprietary chipsets and system designs from HP. In the early 32-bit times workstations (the HP 9000/700s) and servers (HP 9000/800s) used different chipsets; later on, the system platforms of workstations and servers became more similar and used the same chipsets, albeit sometimes in different configurations.

The chipsets were tied to a specific bus architecture but were sometimes used in different generations of systems.

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ASP

Used in

ASP is the chipset used in all older 32-bit PA-RISC workstations with the SGC bus. Still being a classical chipset, ASP includes several different chips to provide the I/O subsystem and several modules from third-party vendors.

There are two variants of ASP:

  1. Coral or Cobra I/O subsystem, the original ASP
  2. Hardball an improved ASP2 variant with fast/wide SCSI and FDDI networking, apparently used only on the 735/755 workstations

Features (ASP)

ASP2 additional features

EISA bridges

Most systems with an ASP chipset feature a separate EISA bus, implemented with the Intel 82350 chipset (82352 EISA buffer, 82357 peripheral and 82358 controller). The EISA adapter is not integrated into or part of ASP but listed here since this configuration was only used with ASP systems.

References

  1. Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal) pp. 6-11
  2. VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) Craig A. Gleason (August 1992: Hewlett-Packard Journal) pp. 12-22
  3. High-Performance Design for Low-Cost PA-RISC Desktops (.pdf) Craig Fink et al (August 1992: Hewlett-Packard Journal) pp. 56-63
  4. Hardball I/O Subsystem, External Reference Specification (.pdf) Hewlett-Packard Company (September 1991, Version 1.1)
  5. The EISA standard for the HP 9000 Series 700 workstations (.pdf) Vicente Cavanna and Christopher S. Liu (December 1992, Hewlett-Packard Journal) pp. 78

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LASI

Used in

Designed for and first used in the HP 9000/712 workstations the LASI I/O controller was designed for cost-reductions. The major objective of the 712 I/O subsystem was to provide similar or equal functionality and performance as other 700 series systems (e.g., 720, 730, 715) at reduced production costs. The integration of major I/O subsystems into one large chip would reduce manufacturing costs significantly. Large parts of the LASI chip are consumed by the logic of the important LAN and SCSI (LASI: LAN SCSI) parts. Both of these designs are third party (NCR and Intel). The other I/O functions are HP-internal standard cell designs, some of whom were taken from previous HP ASIC designs and some designed specifically for LASI. In early systems LASI was used as main I/O controller, in later systems it acted as complimentary part for some of the I/O functions.

Features

References

  1. 712 I/O Subsystem ERS (External Reference Specification) — LASI ERS Hewlett-Packard Company (February 1993, Revision 1.1)
  2. An I/O System on a Chip Thomas V. Spencer et al (April 1995, Hewlett-Packard Journal)

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Wax

Used in

Wax is a secondary I/O controller complimentary to the LASI chipset. It implements various secondary I/O functions and acts as a I/O bus to GSC adapter for different external buses as EISA, HP-HIL and HP-IB. Most systems use it to complement LASI with other needed I/O functions that were previously implented in diverse I/O ASICs. It is implemented in the same process and package as LASI.

Features

References

  1. External Reference Specification (ERS) for the Wax I/O ASIC Hewlett-Packard Company (May 1993, version 1.0 redacted)

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Dino/Cujo

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Dino is the GSC to PCI bridge found in many older PCI PA-RISC workstations. The GSC and PCI buses do not need to be synchronized, simplifying the system design. Dino also implements a small set of I/O functions.

Cujo is a Dino bridge with 64-bit PCI.

Features

References

  1. DINO ERS (External Reference Specification) — A GSC-to-PCI Bridge Hewlett-Packard Company (February 1997, Revision 3.0)
  2. Dino 3.1 (1FC3-0004) Errata Listing Hewlett-Packard Company (September 1997)

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Elroy

Used in

Elroy is the chip used to attach a PCI bus to the system and I/O buses in the various newer PA-RISC systems. Each Elroy chip attaches one PCI bus to one or more of the I/O system’s I/O channels — ropes. Common configurations are one I/O link (about 250MB/s) for one Turbo PCI bus (can have multiple slots or attach multiple I/O devices) or two I/O links (about 500MB/s) for one Twin Turbo bus.

Elroy is also called LBA one some of the newer systems.

Features

References

  1. Elroy ERS (External Reference Specification) — Ropes to PCI Bridge Chip Hewlett-Packard Company (January 2000, Revision A (1.4))

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SIU/SPI

The first PA-RISC processors (PA-RISC 1.0) did not have integrated, unified memory and I/O controllers but used several external support chips to attach the CPU to and control the memory and I/O.

The bus setup and structure was similar on all three NS-1, NS-2 and PCX processors and utilized the SMB CPU attachment but several variants of supports chips.

NS-1:

NS-2:

PCX:

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Viper

Viper is the external single external memory and I/O controller (MIOC) on systems with PA-7000 and PA-7100 processors. The chip is apparently similar on both, and sometimes counted into the ASP I/O chipset.

Viper interfaces with PBus to the processor and VSC to the system main bus. It handles all memory and I/O traffic between the processor and the rest of the system.

Bus attachments

Details

References

  1. Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) pp. 6-11 Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal)
  2. VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) pp. 12-22 Craig A. Gleason (August 1992: Hewlett-Packard Journal)
  3. High-Performance Design for Low-Cost PA-RISC Desktops (.pdf) pp. 56-63 Craig Fink et al (August 1992: Hewlett-Packard Journal)

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Memory and I/O Controller (MIOC)

The Memory and I/O Controller in the PA-7100LC processor and PA-7300LC processor is the integration of both DRAM/cache controller and I/O controller on the processor die. It is very similar on both CPUs, not much has been changed in the transition from 7100LC to 7300LC.

The integrated memory controller requires only buffers and DRAM modules to build up the complete memory subsystem.

On the PA-7300LC the memory controller also includes the SLC (Second Level Cache Controller). It provides an optional L2 cache, ranging from 32KB to 8MB (on almost all systems with a PA-7300LC, 2MB of L2 was used). It shares the data bus with the DRAM subsystem, so it has the same width (64/128-bit) and same optional SEDC error control.

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U2/Uturn

The U2/Uturn I/O adapters (IOAs) attach the I/O adapters and buses (GSC) to the Runway CPU bus on systems with the PA-7200, PA-8000 and PA-8200 processors.

On the I/O side they provide two GSC (HSC) buses to which other I/O chips and bridges or chipsets attach. Systems with PA-7200 use the U2 variant while all later systems the UTurn follow-on.

Details

References

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MMC/SMC

Most systems with a PA-7200, PA-8000 or PA-8200 processor use a combination of the MMC and SMC memory controllers to attach the main system memory to the Runway processor bus. The I/O is controlled by the U2/UTurn I/O adapters on the same Runway bus.

Details

Used in

References

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Astro

Used in

Newer workstations and servers, based on the PA-8500, PA8600 and 8700 processors, use the Astro chip for memory and I/O management (IOMMU). It includes most of the functions on a single die with only few additional peripheral ASICs to interface and drive the specific buses.

Astro attaches to three different buses and is the central part of the chipset:

References

  1. Processor system bus — Runway+/Runway DDR for (theoretically) up to two (apparently four were possible) PA-8x00 processors with a clock of maximum of 125MHz (and peak bandwidth of about 2.0GB/s)
  2. Memory bus with a peak bandwidth of 2.0GB/s at maximum clock of 125MHz
  3. I/O system buses made up from up to eight single I/O links (ropes) which attach to individual PCI bridges — in most cases Elroy chips which convert each one or two I/O links into a PCI bus

There are several different variants of Astro, later ones were called Pluto.

Features

References

  1. Astro External Reference Specification Introduction
    Astro External Reference Specification Error Handling
    Astro External Reference Specification R2I Operations
    Astro External Reference Specification Register Map
    Astro External Reference Specification Runway Interface
    Astro External Reference Specification Memory Map
    Hewlett-Packard Company (February 2000, Revision 1.2)

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Stretch

Used in

Stretch is the chipset or Central Electronics Complex (CEC) used in a very small range of systems. It basically consists of four main components, which build the backbone of the (Runway-based PA-8x00) processor/memory and I/O system — one central memory controller which connects all system buses together; Runway ports for attachment of processors to the system bus; I/O controllers which attach the I/O subsystem to the system bus; PCI bridges, which convert the I/O subsystem’s links into PCI buses:

  1. Prelude SMC memory controller is the central part of the system, it connects the main memory to two system buses (one on each side), to which each one IKE I/O controller and one or more DEW Runway ports (for each two CPUs) attach (Prelude is also called Very Low Latency Memory Controller)
  2. DEW Runway ports/converters convert the Prelude’s system bus(es) (which in fact is an Itanium/Merced bus) into Runway buses for the various CPUs — each two CPUs share one DEW port converter (CPUs from the PA-8500 upwards supported). Common configurations include 1-4 DEWs for up to eight processors.
  3. IKE I/O controllers attach each to the system bus. Common configurations are one IKE for each of the two system buses (one on each side). IKEs then connect to the varios PCI bridges.
  4. Elroy PCI bridges (LBAs) which convert the I/O channels from the IKE I/O controllers into PCI buses, to which the PCI slots and core I/O functions attach. Up to 14 Elroys were used in actual systems.

Features

References

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Cell

Used in

The Superdome and various smaller systems from HP used a cell-based system architecture or Central Electronics Complex (CEC) which was based on interconnecting individual system/processor cells via central crossbars. The cell boards were seated in the backplane of the system, which provided the cell-to-cell links and I/O functionality.

  1. Cell controller (CC): the central chipset and crossbar of these systems. One sits at the centre of each cell board for a maximum of two in the complete system. The CCs provide links for:
    • Up to four Processors (8.0GB/s)
    • Up to two Memory banks (4.0GB/s peak)
    • I/O via SBA (cell to I/O communication is 2.0GB/s peak)
    • PDH (processor dependent hardware) and firmware/flash etc.
    • Second cell via XBC (cell-to-cell communication is 8.0GB/s peak)
  2. Master I/O controller (SBA): the central I/O part of the main chipset, normally one SBA is reserver for each one cell/CC but located on the (I/O) backplane. Each SBA provides sixteen 12-bit links (ropes) — the links/ropes from the SBAs connect to slave I/O controllers (LBAs) which in turn connect the PCI I/O slots and I/O subsystems
  3. Core I/O: provides the standard I/O functions for the system. Made up of cards or card sets, which plug into PCI or special slots and provide third-party I/O functions. Distinct cards were availaible/possible: MP/SCSI card and LAN/SCSI, among others. These cards contain a variety of I/O chips, including Ultra160 SCSI, Ultra2-Wide SCSI, Gigabit Ethernet LAN. Ethernet for management LAN, serial ports for management and console, etc.

Other parts of the chipset are made up from already known components:

References

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