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PA-RISC Chipsets

Overview

Most HP PA-RISC computers used proprietary HP chipsets and system designs. Early 32-bit workstations (HP 9000/700) and servers HP 9000/800) from the 1990s used different chipsets; later on, the system platforms of workstations and servers moved closer and used the same chipsets.

Most chipsets were tied to specific bus architectures but were sometimes used in different generations of systems.

Chipsets used in PA-RISC computers overview
Architecture Chips Bus Usage
Early designs TS-1, NS-1, NS-2, PCX SMB Processor
SIU/SPI SMB CPU bridge/Main bus
CTB SMB, CTB I/O device (bridge)
ASP/Viper PA-7000, PA-7100 PBus Processors
Viper PBus, memory, VSC Memory and I/O controller
ASP VSC, GSC Chipset (I/O)
LASI PA-7100LC, PA-7300LC GSC Processor
MIOC CPU, memory, GSC Memory and I/O controller
LASI GSC Chipset (I/O)
Wax GSC, EISA, HIL, HP-IB Bus bridge to I/O
Dino GSC, PCI Bus bridge to I/O
Cujo GSC, PCI-64 Bus bridge to I/O
U2/UTurn PA-7200, PA-8000,
PA-8200
Runway Processors
MMC/SMC Runway, memory Memory controller
U2 Runway, GSC+ I/O controller
UTurn Runway, GSC2 I/O controller
LASI GSC Chipset (I/O)
Wax GSC, EISA, HIL, HP-IB Bus bridge to I/O
Dino GSC, PCI Bus bridge to I/O
Cujo GSC, PCI-64 Bus bridge to I/O
Astro PA-8500, PA-8600,
PA-8700
Runway+/DDR Processors
Astro Runway, memory, ropes Memory and I/O controller
Elroy Ropes, PCI-64 Bus bridge to I/O
Stretch PA-8500, PA-8600,
PA-8700
Runway+/DDR Processors
DEW Runway, Itanium CPU bridge
Prelude Itanium, memory Memory controller
IKE Itanium, ropes I/O controller
Elroy Ropes, PCI-64 Bus bridge to I/O
Cell PA-8600, PA-8700,
PA-8800, PA-8900
Runway+/DDR Processors
CC Runway, memory,
XBC-cell, SBA link
Processor, memory, I/O controller
XBC XBC-XBC, XBC-cell Crossbar
SBA (RIO) SBA link, ropes I/O controller
LBA (Elroy) Ropes, PCI-64 Bus bridge to I/O
zx1 PA-8800, PA-8900 Itanium 2 Processors
MIO (Pluto) Itanium-2, ropes I/O and memory controller
IOA (Mercury) Ropes, PCI, AGP Bus bridge

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