OpenPA.net

PA-RISC Chipsets

ASP and Viper overview

PA-7000 and PA-7100 systems use the ASP chipset and Viper memory controller. They utilize the VSC CPU/memory, GSC system main and SGC and EISA expansion buses, with servers using HP-PB I/O buses, all provided by separate I/O adapters/bus bridges.

System bus design

View a system-level illustration (ASCII) (single-processor).

Multiprocessor attachment

  1. Two-way SMP (Low Cost): Two CPUs share a PBus and attach to the same MIOC. Memory attaches directly to MIOC, I/O attaches via VSC to MIOC.
  2. Scalable MP: Each CPU has its own MIOC. All MIOCs in the system share a VSC bus, to which I/O and memory attach.

View a system-level illustration (ASCII) (PA-7100 multi-processor).

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ASP

ASP is the chipset used in many older 32-bit PA-RISC workstations with SGC bus and PA-7000 and PA-7100 processors. Being an integrated chipset, ASP includes separate chips to provide the I/O subsystem and contains several modules from third-party vendors.

There are two variants of ASP:

  1. ASP: Coral or Cobra I/O subsystem, the original ASP
  2. ASP2: Hardball, an improved ASP2 variant with fast/wide SCSI and FDDI networking, apparently used only on the 735/755 workstations

Bus attachments

I/O devices

Other features

ASP2 (Hardball) additional features

Used in

References

  1. Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal) pp. 6-11
  2. VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) Craig A. Gleason (August 1992: Hewlett-Packard Journal) pp. 12-22
  3. High-Performance Design for Low-Cost PA-RISC Desktops (.pdf) Craig Fink et al (August 1992: Hewlett-Packard Journal) pp. 56-63
  4. Hardball I/O Subsystem, External Reference Specification (.pdf) Hewlett-Packard Company (September 1991, Version 1.1)
  5. The EISA standard for the HP 9000 Series 700 workstations (.pdf) Vicente Cavanna and Christopher S. Liu (December 1992, Hewlett-Packard Journal) pp. 78

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Viper

Viper is the memory and I/O controller (MIOC) on systems with PA-7000 and PA-7100 processors. The chip is similar on both, and sometimes counted into the ASP I/O chipset.

Viper interfaces with PBus to the processor and VSC to the system main bus. It handles all memory and I/O traffic between the processor and the rest of the system.

Bus attachments

Details

Used in

References

  1. Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) pp. 6-11 Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal)
  2. VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) pp. 12-22 Craig A. Gleason (August 1992: Hewlett-Packard Journal)
  3. High-Performance Design for Low-Cost PA-RISC Desktops (.pdf) pp. 56-63 Craig Fink et al (August 1992: Hewlett-Packard Journal)

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