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PA-RISC Chipsets

Superdome/Cell overview

The Superdome and various smaller systems from HP used a cell-based system architecture or Central Electronics Complex (CEC) which was based on interconnecting individual system/processor cells via central crossbars. The cell boards were seated in the backplane of the system, which provided the cell-to-cell links and I/O functionality.

Cell controller (CC)

CC is the central chipset that sits at the core of each cell. The CC connects to cells local processors and memory to the SBA I/O links and the XBC crossbar.

Bus attachments

Other features

XBC

XBC is the crossbar ASIC of the Cell chipset that providers the main backplane function in the architecture. Each backplane supports up two four cell modules. Different backplanes can be tied together through links through the XBCs with a high-bandwidth, low/latency connection.

M2

M2 are the main memory controllers and converters on each cell board. There are eight M2 controllers that attach in two banks to each CC. Requests and addresses are sent directly from the CC to memory, with the data returning through the M2s.

Bus attachments

RIO (SBA)

RIO is the master I/O controller, also called SBA. The central I/O part of the main chipset, with one SBA reserved for each cell/CC, located on the (I/O) backplane. Each SBA provides sixteen 12-bit links (ropes) to each of which a slave I/O controller LBA connects.

I/O bridges (LBA)

The slave I/O controllers are Elroy PCI bridges (LBAs) that convert the links from the SBA into PCI buses.

Bus attachments

Core I/O

Core I/O is a card set that provides standard I/O functions and plugs into PCI or special slots to provide third-party I/O functions. Distinct cards were availaible: MP/SCSI card and LAN/SCSI, among others.

Bus attachments

Other features

Used in

References

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