PA-RISC Chipsets

Early designs

Early 32-bit PA-RISC systems (1980s TS-1, NS-1, NS-2 and PCX) used custom designs, with most based on the SIU/SPI main bus interfaces attaching the CPU to the SMB bus. In most cases the system processing and I/O units are made up of a large number of individual chips forming the central chipset and using the CIO and HP-PB I/O buses.

  1. System controllers (SIU or SPI) attach the CPU with its execution units to the SMB system main bus
  2. System Main Bus (SMB) is the central bus, to which CPU, memory and I/O buses attach
    • CPU attaches via SIU/SPU to SMB with 64-bit at 25-30 MHz
    • Memory attaches to SMB
    • Some: Memory extensions attach to SMB (via MABs; see below)
  3. Central Bus/Midbus (CTB) attaches the I/O via bus convertes to SMB
    • Attaches via 32-bit at maximum of 10 MHz at SMB
    • Two CTBs per SMB
  4. CIO buses, up to three, attach via adapters to CTB
    • Attaches via 16-bit at 4 MHz (probably dependant on CTB clock)
    • I/O expansion cards plug into CIO slots
  5. Some systems only: Memory Array Buses (MABs) attach to SMB for more memory
    • Attaches via 64-bit (with ECC 72-bit) at SMB

Systems using these early designs (in various, slightly different variants):

View a system-level illustration (ASCII).

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The first PA-RISC processors (1.0) used external support chips to attach the CPU to memory and I/O. This functionality was in later processors integrated into single chips and then moved to the CPU altogether.

The bus setup and structure is similar on NS-1, NS-2 and PCX processors with the SMB CPU attachment but uses different support chips.




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