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PA-RISC Chipsets

LASI overview

PA-7100LC and PA-7300LC systems use the highly integrated LASI chipset, which combines most functions and I/O on a single chip, and an on-CPU MIOC memory controller. These system use GSC or GSC+ as main bus and a variety of expansion buses via bus adapters, ranging from HSC/GSC, EISA to PCI and VME. EISA is provided by Wax, PCI by Dino.

On the two 32-bit LC Low Cost processors PA-7100LC and PA-7300LC GSC is the main system bus. The CPUs integrate the external memory and I/O controller (MIOC) onto the processor (mostly used with LASI chipsets), with memory and cache directly attaching to it.

System bus design

  1. MIOC, main memory and I/O controller, directly integrated on the CPU
    • Execution units and internal caches attach on-chip to the MIOC
    • External cache and memory attach to MIOC
  2. GSC, system main bus, attaches to MIOC and I/O controllers
    • Attaches via 32-bit
    • PA-7300LC systems use extended GSC+
  3. I/O adapters attach to GSC
    • LASI chipset
    • Some video adapters directly attach to GSC
    • I/O slots extend GSC
    • Bus adapters, including EISA, VME and PCI, attach to GSC (includes WAX — a modified LASI —, Dino, and custom chips)

View a system-level illustration (ASCII).

LASI

LASI is an highly integrated chipset primarily designed for cost-reduction while still providing most I/O functions. It was used as the main controller in most PA-7100LC and PA-7300LC systems, while later 64-bit PA-8x00 systems used LASI for complementary I/O functions.

The primary cost reductions were achieved by integrating the major I/O subsystems into a single chip. Large parts of the LASI chip are consumed by the LAN and SCSI controller (LAN SCSI), which both being third party designs (NCR and Intel). Other I/O functions are HP-internal standard designs, some taken over from previous HP ASICs and some designed specifically for LASI. The memory and I/O controller was not contained in the chipset but provided by the on-CPU MIOC on the PA-7100LC and PA-7300LC processors or the main chipset controller in the PA-8x00 systems.

Bus attachments

I/O devices

Other features

Used in

References

  1. 712 I/O Subsystem ERS (External Reference Specification) — LASI ERS Hewlett-Packard Company (February 1993, Revision 1.1)
  2. An I/O System on a Chip Thomas V. Spencer et al (April 1995, Hewlett-Packard Journal)

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Memory and I/O Controller (MIOC)

The Memory and I/O Controller in the PA-7100LC and PA-7300LC processor integrates DRAM/cache and I/O controller onto the processor die. It is similar on both CPUs, with the PA-7300LC MIOC having wider data paths to L2 cache and RAM and supporting the advanced GSC+ bus over the older GSC.

The integrated memory controller requires only buffers and DRAM modules to build up the complete memory subsystem. The PA-7300LC memory controller includes a Second Level Cache Controller (SLC), which provides an optional L2 cache, ranging from 32 KB to 8 MB. It shares the data bus with the DRAM subsystem, so it has the same width (64/128-bit) and same optional SEDC error control.

Bus attachments

Memory

Used in

References

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Wax

Wax is a secondary I/O controller complimentary to the LASI chipset. It implements various secondary I/O functions and acts as a I/O bus to GSC adapter for different external buses as EISA, HP-HIL and HP-IB. Most systems use it to complement LASI with other required I/O functions that were previously implented in diverse I/O ASICs. It is implemented in the same process and package as LASI.

Bus attachments

I/O devices

Other features

Used in

References

  1. External Reference Specification (ERS) for the Wax I/O ASIC Hewlett-Packard Company (May 1993, version 1.0 redacted)

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