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PA-RISC Chipsets

U2/UTurn overview

The PA-7200, PA-8000 and PA-8200 processors with the Runway bus use split I/O and memory controllers — the U2/UTurn I/O Adapters (IOAs) and MMC/SMC memory controllers with each what can be called frontends and backends, with the former interfacing to the CPU and its processor bus and the latter attaching the frontend to customized bus attachments on their external side. This allowed HP to use the frontend parts of these chipsets with a variety of different system design which only required modified backend parts for new memory or I/O technologies.

System bus design

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U2/UTurn

U2 and UTurn I/O adapters (IOAs) attach I/O devices and buses (GSC) to the Runway CPU bus on systems with PA-7200, PA-8000 and PA-8200 processors. On the I/O side they provide two GSC (HSC) buses to which other I/O chips and bridges or chipsets attach.

U2 is the variant for PA-7200 systems while all later systems use the UTurn follow-on.

Bus attachments

Other features

Used in

References

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MMC/SMC

Most systems with a PA-7200, PA-8000 or PA-8200 processor use a combination of the MMC and SMC memory controllers to attach the main system memory to the Runway processor bus. The I/O is controlled by the U2/UTurn I/O adapters on the same Runway bus.

Bus attachments

Memory

Other features

Used in

References

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Dino/Cujo

Dino is the GSC to PCI bridge found in many older PCI PA-RISC workstations. The GSC and PCI buses do not need to be synchronized, simplifying the system design. Dino also implements a small set of I/O functions.

Cujo is a Dino bridge with 64-bit PCI.

Bus attachments

I/O devices

Other features

Used in

References

  1. DINO ERS (External Reference Specification) — A GSC-to-PCI Bridge Hewlett-Packard Company (February 1997, Revision 3.0)
  2. Dino 3.1 (1FC3-0004) Errata Listing Hewlett-Packard Company (September 1997)

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