OpenPA.net

PA-RISC Processors

Introduction

The PA-RISC architecture was the offspring of previous design efforts and lessons that HP learned from developing the FOCUS CPU, the world’s first full 32-bit microprocessor. The FOCUS CPU was at its time (pre-1984) a huge chip (about 450,000 FETs) with a stack-based instruction set. There is a detailed description of the FOCUS architecture on the HP 9000/500 FOCUS page.

The PA-RISC processors were designated to replace the old 16-bit stack-based CPUs in HP 3000 servers and the Motorola 680x0 CPUs in HP’s Unix workstations and servers. Overall PA-RISC was a quite conservative RISC design:

Compared to other RISC architectures from the time, the original PA-RISC design was rather unspectacular — it had typically fewer features but remained always at competitive speeds, especially in Floating Point and SMP (multiprocessing) areas. HP was the first to include multimedia extension in a commercially available microprocessor (MAX-1 in PA-7100LC and MAX-2 64-bit in PA-8000 — similar to Intel’s MMX et al.) which allowed vector operations on two or four 16-bit subwords in 32-bit or 64-bit integer registers.

The original PA-RISC 1.0 architecture included a single instruction/data bus; PA-RISC later on moved to a Harvard-style architecture with seperate instruction and data buses. It has thirty-two 32-bit integer general purpose registers (GR0-GR31), seven shadow registers (SR0-SR6) for fast-interrupts and thirty-two 64-bit Floating Point registers for the FPU, which also could be combined to 64×32-bit and 16×128-bit. The FPU is able to execute a Floating Point instruction simultaneously to the ALU. The original addressing was 48-bit wide, it was later on expanded to 64-bit (with the introduction of the PA-8000 line).1

  1. Great Microprocessors of the Past and Present, John Bayko (June 2001/V 12.1.1: BURKS. Accessed 28 Dec 2007)

↑ up

Overview Table

PA-RISC processor overview
CPU ISA Clock
max		 FETs L1 Cache
max		 L2 Cache
max		 TLB Super
scalar		 SMP Units
TS-1 PA 1.0
32-bit		 8MHz ? 128KB I/D
off-chip		   4K I/D 1-way No 1 Integer
External FPU
NS-1 PA 1.0
32-bit		 30MHz 144k 128KB
off-chip		   4K I/D 1-way No 1 Integer
External FPU
NS-2 PA 1.0
32-bit		 27.5MHz ? 1024KB I/D
off-chip		   16K I/D 1-way No 1 Integer
External FPU
CMOS26B PA 1.0
32-bit		 50MHz 196k 1024KB I/D
off-chip		   8K I/D 1-way Yes 1 Integer
External FPU
PA-7000 PA 1.1a
32-bit		 66MHz 577k 256KB I
256KB D
off-chip		   96 I
96 D		 1-way No 1 Integer
External FPU
PA-7100/
PA-7150		 PA 1.1b
32-bit		 125MHz 850k 1MB I
2MB D
off-chip		   120 2-way Yes 1 Integer
1 Floating Point
PA-7100LC PA 1.1c
32-bit		 100MHz 900k 1KB I
on-chip		 2MB
off-chip		 64 2-way No 2 Integer
1 Floating Point
PA-7200 PA 1.1d
32-bit		 140MHz 1.3M 2KB
on-chip		 1MB I
2MB D
off-chip		 120 2-way Yes 2 Integer
1 Floating Point
PA-7300LC PA 1.1e
32-bit		 180MHz 9.2M 64KB I
64KB D
on-chip		 8MB
off-chip		 96 2-way No 2 Integer
1 Floating Point
PA-8000 PA 2.0
64-bit		 230MHz 4.5M 1MB I
1MB D
off-chip		   96 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
PA-8200 PA 2.0
64-bit		 300MHz 4.5M 2MB I
2MB D
off-chip		   120 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
PA-8500 PA 2.0
64-bit		 440MHz 140M 512KB I
1MB D
on-chip		   160 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
PA-8600 PA 2.0
64-bit		 550MHz 140M 512KB I
1MB D
on-chip		   160 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
PA-8700 PA 2.0
64-bit		 875MHz 186M 768KB I
1.5MB D
on-chip		   240 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
PA-8800
2-core		 PA 2.0
64-bit		 1GHz 300M 2×
768KB I
768KB D
on-chip		 32MB
off-chip		 2×
240		 2×
4-way		 Yes 2×
4 Integer
4 Floating Point
2 Load/Store
PA-8900
2-core		 PA 2.0
64-bit		 1.1GHz 317M 2×
768KB I
768KB D
on-chip		 64MB
off-chip		 2×
240		 2×
4-way		 Yes 2×
4 Integer
4 Floating Point
2 Load/Store
Hitachi
PA/50		 PA 1.1
32-bit		 60MHz 1.28M 8KB I
4KB D
on-chip		   32 I
64 D		 1-way(?) No(?) 1 Integer
1 Floating Point
Hitachi
HARP-1		 PA 1.1
32-bit		 150MHz 2.8M 8KB I
16KB D
on-chip		 512KB I
512KB D
off-chip		 128 I
128 D		 2-way No(?) 1 (2?) Integer
1 Floating Point
  • ISA: Instruction set architecture — version of the PA-RISC architecture and its width, i. e. integer register width and maximum addressable memory (32-bit or 64-bit)
  • FETs: Number of transistors
  • L1/L2 Caches: Maximum amount of Level 1 and Level 2 cache memories — on-chip is integrated onto the CPU die while off-chip cache is implemented with separate chips (most PA-RISC processors supported larger off-chip caches than were implemented in actual products)
  • TLB: (Maximum) size of Transition lookaside buffer memory (in entries)
  • SMP: Capability of the CPU to work in multi-processor configuration
  • Units: Number of functional processing units, for integer and floating point arithmetic, and load/store operations

↑ up

Early PA-RISC

The first PA-RISC processors, designed and used in the mid to late-1980s in the HP 9000/800 servers (and HP 3000 MPE/iX systems), are very poorly documented. Their exact nomenclatura is not clear, one group of sources refers to them as TS-1, NS-1 and NS-2, while other call — apparently the same processors — PN-5, PN-7 and PN-10. These early CPUs still mostly were chipsets — multiple separate chips and components formed the central processing unit (contrary to the mostly single-chip post-PA-7000 implementations). The chips were based on TTL (Transistor-transistor logic), NMOS-III (Negative channel Metal-Oxide Semiconductor), and, lastly, CMOS26B. An interesting aspect of these CPUs are their huge TLB sizes — from 2048 up to 16384 entries, an enormous number of entries when compared to other computers [...] (their successors and competitors had sizes typically in the low to mid hundreds).

TS-1

Used in: 840
Introduced in: 1986

The TS-1 was the very first production processor ot the PA-RISC family and integrated version 1.0 of PA-RISC on six boards (each 8.4×11.3″) of TTL: I-unit (Instruction Unit, controls the instruction flows, executes branches and handles interrupts and traps etc.), Register File Board (contains the 32 32-bit general registers GR0-GR31 and 25 control registers in SRAMs), E-unit (Execution Unit, performs arithmetic and address calculation with the integer ALU, does also load and store operations), TLB (translation lookaside buffer with 4096 entries for 2KB pages), Cache controller (contains the split instruction and data caches — 64KB for each I and D) and FPC (floating-point coprocessor, handles FP operations parallel to the CPU/ALU). Each board contained about 150 ICs. TS-1 processors were only used in the 840 server systems.

NS-1

Used in: 825, 835, 850
Introduced in: 1987

The first implementation of PA-RISC (1.0) in a NMOS fabrication process followed shortly on the original TTL-based TS-1 and was called accordingly NS-1. It implemented the central processing unit on a single chip and needed several other ICs to complete the whole processor (including external FPU and cache chips).

The NS-1 processor is contained on one circuit board (two on 825) and integrates the complete CPU as a single NMOS-III chip, accompanied by eight other (NMOS-III) VLSI chips: SIU (system interface unit), two CCUs (cache controller units CCU0 and CCU1), TCU (TLB controller unit), MIU (math interface unit, which speaks to the FP chips) and three third-party floating point (FP) chips (ADD, MUL and DIV). Cache and TLB memory was implemented in separate chips, their sizes varying on the different computer models — from 16KB up to 128KB cache and TLBs with 2048 up to 4192 entries.

NS-2

Used in: 822, 832, 845, 855, 860
Introduced in: 1989-1990

The last NMOS-based PA-RISC processor was the NS-2, a tweaked follow-on to the NS-1 with increased pipeline stages (from three to five), new TLB and cache controllers and significantly larger caches (1MB) and TLBs (16K).

The NS-2 design was simplified over its NS-1 predecessor. The processor is contained on one processor circuit board and integrates the CPU as a single NMOS-III chip, with seven other VLSI (NMOS-III) chips on its side: SIU (system interface unit), two CCUs (cache controller units, split into instruction and data — ICCU and DCCU), TCU (TLB controller unit), FPC (floating point controller [or coprocessor], speaks to the FP chips) and two third-party floating point (FP) chips (ADD, MULTI). The bus structure connecting these chips was updated (and simplified), with the CPU having private connections to the cache and TLB controllers (for which the NS-1 CPU had to use the shared cache bus).

CMOS26B (PCX)

Used in: 842, 852, 865, 870
Introduced in: 1990?

The last PA-RISC 1.0 design was either called CMOS26B or PCX and was the first PA-RISC processor fabricated in a CMOS process. It implemented the NS-1/NS-2 NMOS-based design in a much more compact CMOS die and integrated several of the processor functions previously supplied on external VLSI chips onto the CPU die. The still needed support chips of the CMOS26B include: three CMUX (cache multiplexer — one instruction, two data; equivalent to the earlier CCUs), SPI (SMB to processor interface — SMB is the system main bus), FPC (floating point coprocessor) and two FP chips (MUL/DIV and ADD/SUB) [not completely clear if the latter two or latter three chips are third-party].

CMOS26B is quite possibly not the correct name of this CPU/chipset. CMOS26B is in fact the name of the HP CMOS fabrication process in which this processor was fabbed. The CMOS26B processor apparently was also called PCX, the CMOS26B just being a reference to its fab process. There are sources which also mention a CS-1 processor — from the nomenclatura this would point to a CMOS-based design but the performance figures/charts do not really match up with the CMOS26B/PCX described here.

References

  1. Wayne E. Holt (ed.), Beyond RISC! An Essential Guide to Hewlett-Packard Precision Architecture (January 1988: Software Research Northwest Inc.)
  2. Hardware Design of the First HP Precision Architecture Computers (PDF) David A. Fotland et al (March 1987: Hewlett-Packard Journal)
  3. HP 3000 Series 950 and HP 9000 Model 850S Family CE Handbook (PDF) Hewlett-Packard Company (October 1990. Accessed January 2008 at hpmuseum.net)
  4. HP 9000 Series 800 Model 825S Hardware Technical Data (PDF) Hewlett-Packard Company (September 1988. Accessed January 2008 at hpmuseum.net)
  5. HP 3000/925 and HP 9000/825/835 Computer Systems CE Handbook (PDF) Hewlett-Packard Company (May 1988. Accessed January 2008 at hpmuseum.net)
  6. New midrange members of the Hewlett-Packard Precision Architecture Computer Family Thomas O. Meyer et al (June 1989: Hewlett Packard Journal. Accessed January 2008 at findarticles.com)
  7. HP 9000 Series 800 Model 822S/832S Technical Data (PDF) Hewlett-Packard Company (1989. Accessed January 2008 at hpmuseum.net)

↑ up

PA-7000 (PCX-S) (Cheetah)

Used in

Time of introduction

1991

Overview

The PA-7000 was the first PA-RISC 1.1 CPU implementation and saw its first uses in the first PA-RISC 700 series workstations and later on in some of the Nova servers. It was still a multi-chip implementation.

Details

References

  1. Various
  2. Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC (PDF) André Seznec and Thierry Lafage (INRIA: June 1997)

↑ up

PA-7100/PA-7150 (PCX-T) (Thunderbird)

Used in

Time of introduction

Early 1992 (PA-7150: 1994)

Overview

The PA-7100 is a superscalar processor that is therefore able to issue more than one instruction at a time. It is the first PA-RISC CPU to integrate the ALU and FPU on a single die thus saving board space and lowering production cost. The communication channel between the PA-7100 and its instruction cache has been doubled which enables this CPU to achieve instruction level parallelism as described above. In this, multiple consecutive instructions are fetched by the CPU and simultaneously dispatched to independent integer and floating point units. Connection to memory and I/O is provided by the external Processor-Memory Interface (PMI) chip, to which the PA-7100 attaches via the P-bus. The PA-7100 is apparently multi-processing capable, with two alternative strategies: either two PA-7100s share the same P-bus to a (shared) PMI, or each PA-7100 is attached to its own PMI, which shares the memory and I/O bus with the other PA-7100/MPIs.
The PA-7150 is a PA-7100 with tweaks to the core and cache subsystem to allow clock frequencies up to 125MHz.

Details

References

  1. Various
  2. Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC (PDF) André Seznec and Thierry Lafage (INRIA: June 1997)

↑ up

PA-7100LC (PCX-L) (Hummingbird)

Used in

Time of introduction

1994

Overview

The PA-7100LC was primarily designed as a single-chip solution for application in low cost systems while still delivering the performance of 1991 high-end workstations and servers. Contrary to earlier PA-RISC version 1.1 implementations which needed several support chips for the MPU the PA-7100LC integrates the CPU, FPU, MIOC (memory and I/O controller) and a first-level cache on a single VLSI chip. Both CPU and FPU support the PA-RISC 1.1 Edition 3 ISA.

Details

  1. Only one of the two integer ALUs is able to handle loads, stores and shifts, these operations can only be paired with simple math operations, like integer addition or multiplication. Both units can handle branch operations.

References

PA7100LC ERS (External Reference Specification) (PDF, 410KB)
Detailed official description of the PA-7100LC processor and its microarchitecture. Hewlett-Packard Company (1999).

↑ up

PA-7200 (PCX-T') (Thunderbird')

Used in

Time of introduction

Early 1995

Overview

The PA-7200 is leveraged from the original PA-7100 design, big parts of the core were just shrunk for the new 0.55 micron CMOS14A process. The FPU was taken over completely unchanged, retaining the same latencies for addition and multiplication even at a higher clock rate. It also acquired the cache design, e.g. had (for the time) big off-chip caches clocked at full CPU speed (140MHz). This chip was aimed at high-performance general-purpose applications but also on specialized applications that used large working sets which could take advantage of the high-bandwidth bus interface.

Details

References

Design of the HP PA 7200 CPU (PDF, 170KB)
Overview on the PA-7200 internals and memory/cache architecture. Kenneth K. Chan et al (February 1996: Hewlett-Packard Journal).
A Different Kind of RISC
PA-7200 general overview. Dick Pountain (August 1994: BYTE Journal).

↑ up

PA-7300LC (PCX-L2) (Velociraptor)

Used in

Time of introduction

Mid 1996

Overview

The PA-7300LC is the direct descendant of the PA-7100LC and likewise designed for low-cost systems. It is still a PA-RISC 1.1 32-bit processor, in contrast to the new PA-RISC 2.0 64-bit PA-8000 introduced in the same timeframe. While the PA-7300LC is rather close to the original PA-7100LC design it has several significantenhancements:

  1. Large on-chip L1 caches (in contrast to the small assist caches of the 7100LC and 7200)
  2. Integrated L2 controller onto the MIOC
  3. Improved bus interface (faster GSC)

The then current process technologies made it possible to include a large L1 cache on the CPU die, breaking a long-standing HP tradition of (large) off-chip L1 caches. The PA-7300LC was the last PA-RISC version 1.1 CPU, all later workstations and servers used 64-bit PA-RISC 2.0 processors.

  1. Only one of the two integer ALUs is able to handle loads, stores and shifts, these operations can only be paired with simple math operations, like integer addition o multiplication. Both units can handle branch operations.

References

PA7300LC ERS (External Reference Specification) (PDF, 716KB)
Detailed official description of the PA-7300LC processor and its microarchitecture. Hewlett-Packard Company (1996).
The PA-7300LC: the first System on a Chip (archive.org mirror)
Presentation prepared for Microprocessor Forum 1995 summarizing the PA-7300LC. Tom Meyer (1996).
The PA 7300LC Microprocessor: A Highly Integrated System on a Chip (PDF, 50KB).
Shorter summary of the PA-7300LC’s design objectives and goals. Terry W. Blanchard and Paul G. Tobin (June 1997: Hewlett-Packard Journal).

↑ up

PA-8000 (PCX-U) (Onyx)

Used in

Time of introduction

January 1996

Overview

The PA-8000 is the first chip to implement the 64-bit PA-RISC 2.0 architecture which includes many extensions to support 64-bit computing. This includes that all integer registers and functional units (ALU, shift/merge) have been widened to 64-bit, i.e. native 64-bit integer arithmetic. The flat virtual address space is 64-bit wide although most PA-RISC version 2.0 CPUs only support a physical address space of 40-bit. Other extensions include fast TLB insert instructions, memory prefetch instructions, support for variable sized pages, branch prediction hinting and FPMAC (Floating Point Multiply Accumulate) units. The instruction decode logic is not integrated with the functional units’ pipeline logic. This architecture allows the chip to partially decode instructions well in advance of the instruction’s actual execution by the functional unit(s).

A key feature of the PA-8000 is the IRB (Instruction Reorder Buffer). Due to restrictions on compiler scheduling, the design team decided that the CPU should perform its own instruction scheduling. The IRB can store up to 28 computation and 28 load/store instructions; it tracks interdepencies between these instructions and allows execution as soon as the instructions are ready. Branch prediction outcomes are also tracked and due to re-scheduling the CPU can execute instructions past cache misses. The IRB is the key part in the OOO execution capabilty of the chip.

In short, the PA-8000 is a decoupled architecture with four-instruction dispatch and aggressive out-of-order (OoO) execution. It has additionally dual floating-point and dual load/store units, a large OOO dispatch window and, following a long HP tradition, no on-chip caches. The (large) primary caches have been kept off-chip to increase the amount of data that can be accessed in a single cycle. Although the latency of the caches is roughly two cycles this can be hidden with complete pipelining resulting practically in one access per cycle. Nothing in the design of this chip was leveraged from previous chip designs.

Details

References

Advanced Performance features of the 64-bit PA-8000 (archive.org mirror)
Detailed description of the PA-8000 innards, presented at CompCon 95. Doug Hunt (1995: IEEE CS Press). [Article reprint for vanished cpus.hp.com]
PA-8000 Combines Complexity and Speed (archive.org mirror)
More general introduction to the PA-8000. Linley Gwennap (1994: Microprocessor Report, Volume 8 Number 15). [Article reprint for vanished cpus.hp.com]
Four-Way Superscalar PA-RISC Processors (PDF, 190KB)
Overview on PA-8000 and its sucessor PA-8200 with an eye on their execution capabilities. Anne P. Scott et al (August 1997: Hewlett-Packard Journal).

↑ up

PA-8200 (PCX-U+) (Vulcan)

Used in

Time of introduction

May 1997

Overview

Shortly after the introduction of the PA-8000 the design team noted several aspects of this chip for improvement in the successor:

The new chip should offer improved performace, compatibility with existing applications and short time to market. The whole design should be heavily leveraged from the existing PA-8000 design foundation.
The availability of new 4Mb SRAMs with faster access times allowed an increased CPU clock-speed and a bigger cache size. Furthermore the team analyzed that the PA-8200 performance could be enhanced significantly if wasted cycles while waiting for instructions and data were reduced. Due to this, it was concluded that increasing the BHT, TLB and caches are high benefit, low risk improvements.

Details

References

Four-Way Superscalar PA-RISC Processors (PDF, 190KB)
Overview on PA-8000 and its predecessor PA-8200 with an eye on their execution capabilities. Anne P. Scott et al (August 1997: Hewlett-Packard Journal).
HP Pumps Up PA-8x00 Family (archive.org mirror)
Description and results of the improvements made in PA-8200 and PA-8500. Linley Gwennap (October 1994: Microprocessor Report, Volume 10 Number 14). [Article reprint for vanished cpu.hp.com]

↑ up

PA-8500 (PCX-W) (Vulcan)

Used in

Time of introduction

September 1998

Overview

The PA-8500 is a direct evolution of the PA-8000 and PA-8200 processors; the processing core was taken over incorporating only minor changes. However, for the first time in a PA-RISC CPU, a large L1 cache was integrated directly onto the CPU die, breaking with a long-standing HP tradition of keeping the L1 caches off-chip (although the two years older PA-7300LC processor already included an albeit smaller L1 cache on-chip). Some of the other improvements include bigger TLB and BHT. The PA-8500 is a full 64-bit chip and as such supports a flat 64-bit virtual address space, although only 40 physical address bits are used by the chip, corresponding to one Terabyte of directly addressable memory. Backward compatibility to older 32-bit PA-RISC CPUs is provided.

The big challenge in developing the PA-8500 was its huge on-chip cache. It had to fit onto the allocated die area and be able to keep up with the IRB. A similar cache design to that of its predecessors was used, although the RAM cells for the cache now sat directly on the die. The data cache is composed of 0.5MB banks, implemented with four 0.125MB arrays providing error correction. The data is organized in such way that either a full cache line can be addressed at once or four ways of associativity together. The instruction cache is implemented as one bank of 0.5MB four-way set associative pipelined cache, providing 128 bits of instruction plus pre-decode bits per cycle.

As his predecessors the PA-8500 is able to execute instructions speculatively; the processor guesses the path of the ongoing instructions and executes them in this path. If the guess is found to be incorrect, the speculatively executed instructions are discarded. Speculative execution is aided by a branch prediction mechanism based on the branch history table (BHT).

Details

References

HP Pumps Up PA-8x00 Family (archive.org mirror)
Description and results of the improvements made in PA-8200 and PA-8500. Linley Gwennap (October 1994: Microprocessor Report, Volume 10 Number 14). [Article reprint for vanished cpu.hp.com]
A 500 MHz 1.5 MByte Cache with On-Chip CPU (PDF, 141KB)
Slides of a presentation on the PA-8500 CPU. Jonathan Lachman and J. Michael Hill (1997: ISSCC).
PA-8500: The Continuing Evolution of the PA-8000 Family (archive.org mirror)
Description of PA-8500 development and technical details. Gregg Lesartre and Doug Hunt (1997: Proceedings of CompCon, IEEE CS Press). [Article reprint for vanished cpu.hp.com]

↑ up

PA-8600 (PCX-W+) (Landshark)

Used in

Time of introduction

January 2000

Overview

The PA-8600 basically was just a PA-8500 with minor modifications to make it fit onto a new manufacturing process in order to achieve higher clock speeds. One of the only real changes applied to the original design was a quasi LRU replacement policy for the instruction cache. Moreover, the interface to the Runway bus apparently was slightly modified, and the order of the bus transaction reworked.

Details

↑ up

PA-8700 (PCX-W2) (Piranha)

Used in

Time of introduction

August 2001

Overview

The PA-8700 is basically an enhanced and revamped PA-8500 core with some slight modifications. As all PA-8x00 CPUs before, it logically still is very close to the original PA-8000 core from 1997. All subsequent new CPUs from HP were based on this design and added several features and some slight modifications to it while retaining the basic PA-RISC version 2.0 core. The PA-8700 enhanced the on-chip L1 caches and the TLB significantly while switching to a new CMOS-process helped boosting the clock-frequency. The chip was at its time one of the largest available commercial CPUs and one of the first to be manufactured in a SOI (Silicon On Insulator) process. The PA-8700 was manufactured by IBM, in contrast to the PA-8500 and PA-8600, which were fabbed by Intel, after HP gave up its processor fabs long time ago.

Details

References

A 900MHz 2.25MByte Cache with On Chip CPU (PDF, 119KB)
Slides of a presentation on the PA-8700 CPU, centered on the CPUs cache subsystem. J. Michael Hill and Jonathan Lachman (2000: ISSCC).

↑ up

PA-8800 (PCX-?) (Mako)

Used in

Time of introduction

2004

Overview

The PA-8800 integrates two PA-8700 cores onto a single die, adds a very large off-die L2 cache (though with a very significant bandwidth) onto the CPU module, enhances the clock frequency a bit further and uses the Itanium/McKinley processor/system bus. Mako was supposed to breathe fresh life in the PA-RISC line, though it had strong internal competition from the Itanium line (based on much HP development; with Intel) and as such was not marketed much. Most systems which could handle a PA-8800 use the HP zx1 chipset and could be hardware-upgraded to use Itanium 2/IA64 processors.

Details

References

HP’s Mako Processor (PDF, 1.4MB)
Slides of a presentation on the PA-8800 CPU. David J. C. Johnson (2001: Microprocessor Forum).

↑ up

PA-8900

Used in

Time of introduction

2005

Overview

The PA-8900 is a slightly tweaked PA-8800 featuring a doubled L2 cache and a higher clock frequency. It is probably the last processor of the PA-RISC family, no more new PA-8x00s will be released. Future systems will be based around Itanium-family chips, although since HP dropped its line of Itanium-based workstations it seems the PA-8900-powered C8000 workstation will be one of the last HP-UX workstations (together with the similar Itanium-based zx2000).

Information on the PA-8900 is generally scarce, it seems there was not much interest releasing many details on the inner workings and architecture, no whitepapers or more detailed articles could be found.

Details

References

Overview of the HP 9000 rp3410-2, rp3440-4, rp4410-4, and rp4440-8 Servers (PDF, 700KB)
Technical Whitepaper from HP on new servers and the PA-8900 processor. Hewlett-Packard (2005).

↑ up

Hitachi PA/50

Used in

Time of introduction

About 1993

Overview

The PA/50 was a PA-RISC version 1.1 compatible processor designed and manufactured by Hitachi. Two designs were developed: M and L, the latter being the lower-cost product. They were meant as personal workstation or high-end embedded controllers. Hitachi integrated a set of previously features not existing (at that time) in any PA-RISC CPU,e.g. on-chip caches, data-prefetching, a power-saving mode and SDRAM support.

Details

References

PROgress (PA-RISC) Newsletter - comp.sys.hp
Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)

↑ up

Hitachi HARP-1

Used in

Time of introduction

June 1994

Overview

The HARP-1 was a PA-RISC version 1.1 compatible CPU from Hitachi; apparently a larger, faster version than the above PA/50 (sadly not much information available).

Apparently the HARP-1E model of this processor includes (pseudo) vector processing modifications/add-ons and was used in Hitachi vector/supercomputers. It seems the L1 cache was also increased to 16 KB/16 KB of instruction and data.

Details

References

  1. Chronology of Workstation Computers (1993) Ken Polsson (November 2007. Accessed November 2007)
  2. PROgress (PA-RISC) Newsletter - comp.sys.hp Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)
  3. Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1 (PDF) Hidekazu Terai et al (October 1999: Hitachi Ltd. Accessed January 2008)

↑ up

Other Processors

Winbond W89K

Time of introduction: Spring 1994

Winbond introduced an embedded PA-RISC controller chip in 1994 — the Winbond W89K. The chip was pin-compatible with the then-popular Intel 80486DX and thus could be used as a drop-in replacement in mid-1990s PCs together with Winbond BIOS replacement chips. Rationale at that time was to allow hardware developers utilize existing 486DX mainboards and components for a shorter product development lifecycle. The W89K was a level 0 PA-RISC 1.1 implementation: a 32-bit PA-RISC processor however without support for virtual addressing.

References

PROgress (PA-RISC) Newsletter - comp.sys.hp
Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)
Winbond, Varian sign deal for thin-film IC process
Terho Uimonen (April 1994: Electronic News. Accessed January 2008 at findarticles.com)
PA-RISC in a PC box (was: Re: HP's vision of a low-end 3000) - comp.sys.hp.mpe
Stan Sieler (Februar 1996. Accessed December 2007)

↑ up

Winbond W90210 | W90215

Time of introduction: Fall 1997

Shortly after the W89K embedded controllers Winbond apparently also introduced a more sophisticated PA-RISC processor in the W90K line of embedded controllers. The W90210F still was a 32-bit PA-RISC 1.1 design, but integrated many external I/O components on the chip — DRAM and DMA controllers, a PCI bridge and various I/O ports. As its predecessor the W90210F was also a level 0 PA-RISC 1.1 implementation: no virtual addressing. It apparently was used in Internet appliances: set-top boxes, TV sets, DVD players, PDAs, VoIP devices, and also for industrial automation. The W90215 is identical to the W90210 but did not include license rights for the embedded operating system (and was thus cheaper).

References

W90210F PA-RISC Embedded Controller (.pdf)
Winbond Electronics Corp. (October 1997. Accessed January 2008)

↑ up

Winbond W90220 and W90221

Time of introduction: Spring 1999

The W90220F is, as its predecessor W90210 a 32-bit PA-RISC 1.1 design without MMU (level 0), but integrated many external I/O components on the chip — DRAM and DMA controllers, PCI bridge, IDE channels, I/O ports and, on the W90221, even an integrated graphics/TV chip. It had the same target systems, set-top boxes and internet appliances. The sucessor W90221 is apparently very similar with higher clock speed, integrated (S)VGA and TV controller

References

W90220F PA-RISC Embedded Controller (.pdf)
Winbond Electronics Corp. (March 1999. Accessed January 2008)

↑ up

Oki OP32

Oki Semiconductors OP32/50N was introduced in 1994 as a embedded controller, based on a 32-bit PA-RISC design with integrated DRAM and DMA controllers. The chip was targeted at laser printers, Fax machines, X-Terminals and the Telecom and Automotive markets.

References

PROgress (PA-RISC) Newsletter - comp.sys.hp
Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)

↑ up

← back to hardware