The computers covered by this site are based on PA-RISC processors, implementing the PA-RISC architecture, connected by various buses to the system chipsets, with I/O handled by SCSI controllers and video adapters.
The following systems design and components were used between the 1980s and mid-2000s. Most of the chips used were HP designed, including the processors, chipsets, memory controllers and the overall system design. Some of the I/O controllers were third-party, but the rest was designed and produced in-house.
Early Precision Architecture, late 80s
PA-RISC was started in the 1980s, as an outgrow of HP research into RISC with the name
The earliest systems from the mid-1980s used 32-bit PA-RISC 1.0 (TS-1, NS-1, NS-2 and PCX) and custom HP designs, with most based on the SIU/SPI main bus interfaces attaching the CPU to the SMB bus. In most cases the system processing and I/O units are made up of a large number of individual chips or boards forming the central chipset with the CIO and HP-PB I/O buses. These are grouped as Early system designs.
Major innovations and developments took place from the late 1980s to the early 1990s to produce the PA-RISC 1.1 architecture and popular Unix systems based on it from the early 1990s on. They did not have much in common with the early PA-RISC 1.0 systems.
The PA-RISC heydays in the 1990s
Along with the architecture, PA-RISC hardware designs matured throughout the early 1990s, with popular 32-bit PA-7000 and PA-7100 systems using the ASP chipset and Viper memory controller. They utilize the VSC CPU/memory, GSC system main and SGC and EISA expansion buses, with servers using HP-PB I/O buses, all provided by separate I/O adapters/bus bridges. (ASP/Viper-based system designs)
From the mid-1990s on, the integrated,
low-cost PA-7100LC and PA-7300LC
systems use the highly integrated LASI chipset,
which combines most functions and I/O on a single chip, and an on-CPU
MIOC memory controller.
These system use GSC or GSC+ as main bus and a variety of expansion buses via
bus adapters, ranging from HSC/GSC, EISA to PCI and VME.
EISA is provided by Wax, PCI by Dino.
(LASI system designs)
PA-7200 and 64-bit PA-8000 and some PA-8200 systems use the U2/Uturn I/O adapters, which attach two GSC/HSC buses to the main Runway bus, and MMC/SMC memory controllers. I/O is realized on the GSC bus with the LASI chipset and Wax and Dino I/O adapters. (U2/Uturn system designs)
64-bit to Itanium in the 2000s
PA-RISC computers from the turn of the century used 64-bit PA-8500, PA8600
and PA-8700 designs with a
rope-based architecture with Astro as main system controller and
separate Runway+/Runway DDR buses with I/O devices controlled by Elroy
These are the Astro-based system designs.
Midrange servers from that time are based on the same processors (PA-8500 to 8700) but use the sophisticated Stretch chipset, a rather complicated setup with central system controller and links to separate processor and I/O controllers and PCI bridges. Main system bus is the Itanium bus, with converters for the processors’ Runway+/Runway DDR buses. These are Stretch system designs.
mainframes and similar servers are based on PA-8700 and PA-8800/PA-8900
processors and use the Cell chipset, similar to the Stretch, but more scalable.
Systems are made up of
cells, with their own central system/memory controller, I/O
controller and PCI bridges.
Grouped together as Cell-based architecture.
The last PA-RISC systems before the mainstream advent of the Itanium VLIW architecture in the mid-2000s use PA-8800/PA-8900 processors, followed by several generationis of Itanium systems. Both use the HP zx1 chipset, conceptually similar to Astro systems but with higher datarates and options, based on Itanium 2/McKinley buses. These are zx1, Itanium-like system designs.
Several pages with older and abandoned PA-RISC content are kept on this site for archival reasons . They are listed on Archived PA-RISC pages. There is also a page on official HP documents that have since disappeared from the web.