PA-RISC Processors
PA-7000 (PCX-S)
Overview
The PA-7000 was a 32-bit PA-RISC processor, version 1.1 architecture with a MMU, introduced in 1991. It was first used in the HP 9000 700 series workstations and later in some of the HP 9000 800 Nova servers. The PA-7000 was a multi-chip implementation with an external FPU.
Details
- PA-RISC version 1.1a, 32-bit architecture
- Two functional units: 1 integer ALUs, 1 external FPU
- Five-stage pipeline
- TLB: 192 in I/D; BTLB: 8 in I/D
- Cache L1 256 KB I and 256 KB D off-chip
- Memory and I/O controllers are external
- PBus processor bus, 32-bit, from processor to the Memory and I/O Controller MIOC
- Up to to 66 MHz closck speed with 5.0 V core voltage
- 14.2×14.2 mm2 die, 577,000 FETs, 1.0µ, 2-layer CMOS26B in 408-pin CPGA
- External FPU fabbed in 13.0×13.0 mm2 die, 640,000 FETs, 0.8µ, TI EPIC-2 in 207-pin CPGA
Used in
- HP 9000 705, 710, 720, 730, 750 workstations
- HP 9000 F10, F20, F30, G30, G40, H20, H30, H40, I30, I40 servers
- HP 9000 890 mainframe
- Mitsubishi ME/R7200, ME/S7200, ME/R7300, ME/S7300, ME/R7500, ME/S7500 workstations
References
- Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC (PDF) André Seznec and Thierry Lafage (INRIA: June 1997)
- Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) pp. 6-11 Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal)
- VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) pp. 12-22 Craig A. Gleason (August 1992: Hewlett-Packard Journal)