PA-RISC Processors


The first PA-RISC processors were designed and used in mid to late-1980s in early HP 9000/800 servers and HP 3000 MPE/iX systems. The exact naming scheme is not totally clear as some sources refers to these processors as TS-1, NS-1 and NS-2 while others call apparently the same processors PN-5, PN-7 and PN-10. These early CPUs still mostly were multi-chip processors with separate chips and components forming the central processing unit, contrary to the mostly single-chip post-PA-7000 implementations. The chips were based on TTL manufacturing, then NMOS-III and finally CMOS26B. An interesting aspect of these CPUs is their huge TLB — from 2048 up to 16384 entries while their successors and competitors had sizes typically in the low to mid hundreds.


The TS-1 was the first PA-RISC production processor, introduced in 1986. It integrated version 1.0 of PA-RISC on six 8.4×11.3″ boards of TTL and was used in HP 9000 840 servers, the first PA-RISC computers.

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The first implementation of PA-RISC in a NMOS fabrication process, NS-1, followed in 1987 shortly after the original TTL-based TS-1. The NS-1 processor is integrated on a single circuit board (two on 825 servers) with the CPU as single NMOS-III chip supplemented by external support chips. It was used in: HP 9000 825, 835, 850 servers.

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The final NMOS PA-RISC processor was the NS-2, a tweaked follow-on to the NS-1 introduced in 1989-90 with from three to five stages increased pipeline, new TLB and cache controllers and significantly larger caches and TLB. The NS-2 is implemented on one circuit board with the CPU as a single NMOS-III and seven other VLSI chips. The bus structure connecting these chips was updated and simplified, with the CPU having private connections to the cache and TLB controllers, for which the NS-1 CPU had to use the shared cache bus.

The NS-2 was used in the HP 9000/822 and 832 and the 845, 855, 860 servers.

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The last PA-RISC 1.0 design was the PCX, introduced 1990 and the first PA-RISC processor fabricated in a CMOS process. It implemented the NS-1/NS-2 design and several of the processor functions previously supplied on external VLSI chips onto a single CPU chip. The PCX was also supplemented by external support chips, including three cache multiplexers, the SPI main bus to processor interface, an floating point coprocessor and two FP chips for MUL/DIV and ADD/SUB. The successor to the PCX was the PA-RISC 1.1 PCX-S or PA-7000 processor, which integrated most processor logic minus the FPU onto a single die/chip

PCX was used in the HP 9000/808, 815 and HP 9000/842, 852, 865, 870 servers.

Some sources that mention a CS-1 processor — CS would point to a CMOS design but the performance figures and diagrams do not really match up with the CMOS26B/PCX described here.


  1. Wayne E. Holt (ed.), Beyond RISC! An Essential Guide to Hewlett-Packard Precision Architecture (January 1988: Software Research Northwest Inc.)
  2. Hardware Design of the First HP Precision Architecture Computers (PDF) David A. Fotland et al (March 1987: Hewlett-Packard Journal)
  3. HP 3000 Series 950 and HP 9000 Model 850S Family CE Handbook (PDF) Hewlett-Packard Company (October 1990. Accessed January 2008 at
  4. HP 9000 Series 800 Model 825S Hardware Technical Data (PDF) Hewlett-Packard Company (September 1988. Accessed January 2008 at
  5. HP 3000/925 and HP 9000/825/835 Computer Systems CE Handbook (PDF) Hewlett-Packard Company (May 1988. Accessed January 2008 at
  6. New midrange members of the Hewlett-Packard Precision Architecture Computer Family Thomas O. Meyer et al (June 1989: Hewlett Packard Journal. Accessed January 2008 at
  7. HP 9000 Series 800 Model 822S/832S Technical Data (PDF) Hewlett-Packard Company (1989. Accessed January 2008 at
  8. A 30 MIPS VLSI CPU, Brian D. Boschma et al (ISSCC 89: February 1989)

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